Logic Gate Assignment Help
Q1:In which of the following base systems is 123 not a valid number?
(a) Base 10
(b) Base 16
(d) Base 3
Q2:.A NAND gate is called a universal logic element because
(a) it is used by everybody
(b) any logic function can be realized by NAND gates alone
(c) all the minization techniques are applicable for optimum NAND gate
(d) many digital computers use NAND gates.
Q3: Most of the digital computers do not have floating point hardware because
(a) floating point hardware is costly
(b) it is slower than software
(c) it is not possible to perform floating point addition by hardware
(d) of no specific reason.
Q4: Positive logic in a logic circuit is one in which
(a) logic 0 and 1 are represented by 0 and positive voltage respectively
(b) logic 0 and, -1 are represented by negative and positive voltages respectively
(c) logic 0 voltage level is higher than logic 1 voltage level
(d) logic 0 voltage level is lower than logic 1 voltage level.
Q5: Among the logic families, the family which can be used at very high frequency
greater than 100 MHz in a 4 bitsynchronous counter is
Q6: SR Flip flop can be converted to T-type flip-flop if ?
(a) S is connected to Q
(b) R is connected to Q
(c) Both S and R are shortened.
(d) S and R are connected to Q and Q’ respectively
Q7: Register is a?
(a) Set of capacitor used to register input instructions in a digital computer
(b) Set of paper tapes and cards put in a file
(c) Temporary storage unit within the CPU having dedicated or general purpose
(d) Part of the auxiliary memory
Q8: For which of the following flip-flop the output clearly defined for all combinations
of two inputs?
(a) Q type flip-flop
(c) R S type flip-flop
(b) J K flip-flop
(d) T flip-flop
Q9: What is a digital-to-analog converter?
(a) It allows the use of cheaper analog techniques, which are always simpler.
(b) It takes the digital information from an audio CD and converts it to a usable
(c) It converts direct current to alternating current.
(d) It stores digital data on a hard drive.
Q10: The output of an OR gate is LOW when ________.
(a) all inputs are LOW
(c) any input is LOW
(b) any input is HIGH
(d) All inputs are HIGH
Q11: (a) What are minterms and maxterms? Minimize the Boolean function F=(X+X’ .Y)
(b) Minimise the following problems using the Karnaugh maps.
(i) X = f(A,B,C) = A’B’C’ + A’B + ABC’+AC
(ii) X = f(A,B,C) = A’B + BC’ + BC + AB’C’
Q12: (a) Show how a full-adder can be converted to a full-subtractor with the addition
of one inverted circuit.
(b) Design a combinational circuit to convert a 8-4-2-1 code to excess-3 code.
Q13: (a) Explain the different triggering techniques of flip-flops.
(b) Explain the working of a T flip flop.
Q14: Discuss the following in detail:
(a) Shift-registers. (b) Multiplexers.
Q15: (a) Design four-bit ring counter using D flip-flops.
(b) Discuss the differences between combinational circuits and sequential circuits.
Q1. (a)Obtain the logic diagram of a master- slave J-K flip flop with AND and NOR gates.
(b) Design a counter with the following binary sequence 0,1,3,7,6,4 and repeat .use T flip-flop.
Q2. (a)What is mantissa and exponent ? Give suitable example.
(b) Design a 6-bit ring counter using J-K flip-flops
Q3. (a) Answer the following.
(1) What do you mean by minterm&maxterm
(2) What is a four bit binary parallel adder ? .
(b) Design a counter with following binary sequence 0,1,4,2,6 and repeat .Use JK flip-flop.
Q4. (a) Design a MOD-18 ripple counter using J-K flip-flop.
(b) Give the block diagram of processor unit and explain the function of different blocks.
Q5. (a) An eight –bit binary ripple UP counter with a modulus of 256 is holding the count 01111111 what will be the count after 135 clock pulses be ?
(b) Design a logic diagram for an addition /subtraction circuit, using a control variable P such that this operates as a full –adder when P=0 and as a full-subtractor for P=1
Signals & Systems
Q1 State whether the following statements are true or false and justify your
- The series interconnection of two linear time-invariant systems is itself a
linear, time-invariant system?
(b) The series interconnection of two nonlinear systems is itself nonlinear?
Q2 A particular first-order casual and stable discrete-time LTI system has a step
response whose maximum overshoot is 50% of its final value. If the final value is
1, determine a difference equation relating the input x[n] and output y[n] of this
Q3 The Laplace transform X(s) of a signal x(t) has four poles and an unknown
number of zeros. The signal x(t) is known to have an impulse at t = 0. Determine
what information, if any, this provides about the number of zeros and their
Q4 Let x(t) be a signal that has a rational Laplace transform with exactly two poles,
located at s = -1 and s = -3. If g(t) = e2t x(t) and G (jw) [ the Fourier transform of
g(t)] converges, determine whether x(t) is left sided, right sided, or two sided?
Q5 Let x[n] be an absolutely summable signal with rational z-transform X(z). If X(z)
is known to have a pole at z= ½, could x[n] be
- a finite-duration signal?
- a left-sided signal?
- A right-handed signal?
- A two-sided signal?
Q6 Consider a feedback system, either in continous-time or discrete-time, and suppose that the Nyquist plot for the system passes throughthe point -1/K. Is the feedback system stable or unstable for this value of the gain? Explain your answer?
Q1 (A) WICH IS THE FASTEST ADC AND WHY?
(B) HOW MANY LEVELS ARE POSSIBLE IN A TWO-BIT DAC?WHAT IS IT’S RESOLUTION IF THE OUTPUT RANGE IS 0 TO 3 V?
Q2 (A) WHAT IS THE RANGE OF MODULATING INPUT VOLTAGE APPLIED TO A VCO?
(B) DRAW THE CIRCUIT OF A PLL AM DETECTOR AND EXPLAIN IT’S OPERATIONS.
Q3 (A) GIVE THE CONVERSATION TIME FOR
(1) COUNTING ADC
(2) SUCCESSIVE APPROXIMATION ADC
(3) DUAL-SLOPE ADC.
(B) SHOW WITH THE HELL OF CIRCUIT DIAGRAM AN OP-AMP USED AS
(i) SCALE SCHANGER,
(ii) PHASE SHIFTER,
(iii) INVERTING ADDER
(iv)NON INVERTING ADDER.DRAW AN OP-AMP CIRCUIT WHOSE OUTPUT IS V1+V2-V3-V4.
Q4 (A) WHAT ARE THE MODES OF OPERATIONS OF A TIMER?
(B) WHAT IS THE PRINCIPLE SWITCH MODE POWER SUPPLIES?DISCUSS IT’S ADVANTAGES AND DISADVANTAGES.
Q5 (A) DESIRE THE TRANSFER FUNCTION OF A SECOND ORDER BP FILTER USING OTA’S.
(B) EXPLAIN THE OPERATION OFFER SQUAR WAVE GENERATOR BYE DRAWING THE CAPACITOR AND OUTPUT VOLTAGE WAVEFORMS.
Q6 (A) LIST THE NON-IDEAL dc CHARACTERISTICS OF AN OP-AMP.
(B) WHAT IS BODE PLOT?
(C) WHAT ARE THE DIFFERENT LINEAR ICPACKAGES?
(D) NAME THE TECHNOLOGY USED FOR THE FABRICATION OF TRANSISTORS OR ICS.