Internal block diagram of the BERT System

Figure 1a – Top-level block diagram of BERT system

The physical layout of the BERT system implemented using the Digilent® ‘Basys3’ development board, shown in figure 1b, illustrates the location of the main inputs and outputs. Eight sliding switches (SW0…SW7) are used to set the delay value when synchronising the transmitted and received data bits, while switches SW12 to SW15 are used to control error insertion.

A wire link is shown connecting ‘man_tx’ to ‘man_rx’ at the top right hand 10-way connector JB1, this constitutes the so-called ‘loop-back’ configuration.

Error  onErrRate2ErrRate1ErrRate0



Internal block diagram of the BERT System




Delay Switches

Figure 1b – Physical layout of BERT system

Figure 1c, below, shows the internal block diagram of the Bit Error Rate Tester System.


Pcount[9:0]Display DriverA[0:3]







Figure 1c – Internal block diagram of the BERT System

The system is made up of four main blocks, the majority of which are clocked by the system clock input (‘clock’) and asynchronously reset by means of the ‘rst’ input push-button. A Display Driver logic circuit outputs the ‘Match Count’ value to the multiplexed 4-digit, 7-segment display. All of the blocks in Figure 1c are SystemVerilog modules and, with the exception of the ‘Sync_control’ block, contain instances of sub-modules. Wherever possible, the names of ports and interconnecting signals should be kept the same in order to exploit the automatic port connection feature of the SV language.

The system provides additional outputs ‘nrz’ and ‘man_bit_clk’ for testing purposes only, the Manchester encoded data bits being transmitted are on output ‘man_tx’.

The Manchester Transmitter block contains a sub-module that allows errors to be inserted into the transmitted data stream corresponding to a range of bit-error rates from 1% to 50%, this allows the BERT system to perform self-testing when performing a so-called ‘loop-back’ test, i.e. ‘man_tx’ linked directly to ‘man_rx’.

Task 1 – Create a SV source descriptions for the ‘ManchTrans’ block

The timing diagram of figure 2a below shows the behaviour of the signals associated with the Manchester Encoding block (assuming the error insertion logic is disabled). The NRZ data stream is to be a Pseudo-Random Bit Sequence (PRBS) containing (2N – 1) bits, where ‘N’ is a parameter that sets the length of the PRBS shift register (set to 10 for implementation). The sequence continually repeats without interruption (apart from when the global system reset (rst) is asserted).

The 100MHz main system clock is to be divided internally by 10 to result in a data bit rate of 10MBits/second. This achieved by means of an internal signal, ‘bit_en’ (bit enable), that pulses high for one clock period every 10, as shown by the red waveform in figure 2a.

Figure 2a – Timing Waveforms for Manchester Encoding

Figure 2b shows the internal block diagram of the ‘ManchTrans’ block.




Figure 2b – Internal structure of the ‘ManchTrans’ block

As shown in the above diagram, a sub-module named ‘divclk’ generates the three basic timing signals (‘bit_en’, ‘bit_clk’ and ‘tbe’ in figure 2a) from a 4-bit, divide-by-10 counter signal (‘count’). Given that the signal ‘count’ goes from 0 to 9 repetitively:

‘bit_en’ is logic-1 when count equals 9

‘bit_clk’ is logic-1 when count is in the range 0 to 4 inclusive ‘tbe’ is logic-1 when count equals 4

Create a SV module for the clock divider ‘divclk’ having the module header provided below.

module divclk #(parameter DIVIDER = 10, N = 4)

input logic clock,

input logic rst,         //asynchronous reset

output logic bit_en,

output logic bit_clk,

output logic tbe);

The parameters ‘DIVIDER’ and ‘N’ allow the division ratio to be changed if necessary, ‘N’ being the length of the register required to divide by ‘DIVIDER’.

Create a Vivado® RTL project setup to target the FPGA device on the Basys3 development board (xc7a35tcpg236-1). Add the ‘divclk’ design source file you have created in task 1 to the project, making sure it is associated with both implementation and simulation. Verify correct operation of the ‘divclk’ module by performing an interactive behavioural simulation using the Vivado Simulator, you will need to set the ‘divclk’ module as the top-level simulation source if there are other sources in the simulation group. Add the relevant signals to the wave window and use the ‘Force’ commands to stimulate the inputs (Right click over signal name in waveform window and: ‘Force – Clock’/’Force – Constant’).

Capture the waveform results in order to clearly show correct operation of the module and insert them, along with the source listing, into your report. Comment on the results obtained.[10 marks]

The output ‘bit_en’ from the ‘divclk’ module enables the pseudo-random bit sequence generator (prbsgen) to shift out the next random data bit on signal ‘prbs’ every 10 clock pulses, whilst also incrementing ‘Pcount’ by 1. The signal ‘Pcount’ keeps track of the number of bits output during each burst of pseudo-random bits. This count value can be reset to zero at any time by asserting the input ‘clr_pcount’, this occurs synchronously at the next positive-edge of the clock. Note that the PRBS data bit sequence is not affected by clearing ‘Pcount’.

The following image in figure 2c shows the ‘prbs’ and ‘Pcount’ output waveforms of the ‘prbsgen’ module (bottom 2). Both outputs ‘prbs’ and ‘Pcount’ are triggered by input ‘bit_en’ and the corresponding system clock edge.Figure 2c – Timing waveforms for outputs of ‘prbsgen’The following partial listing is an outline of the ‘prbsgen’ SV description. Parameter ‘N’ sets the length of both the pseudo-random bit sequence register (prbsreg) and the data bit counter ‘Pcount’. Parameter ‘TapMask’ selects the bits of the pseudo-random bit sequence register that are Exclusive-Or’ed and fed back to the input of the least significant flip-flop (feedback taps).

module prbsgen #(parameter N = 8, TapMask = 8’b11100001)

(input logic clock, rst, bit_en, clr_pcount,

output logic prbs,

output logic [N-­‐1:0] Pcount);

logic [N-­‐1:0] prbsreg;  //pseudo-­‐random bit sequence register

always_ff @(posedge clock, posedge rst)


if (rst) begin

//insert asynchronous reset action

end else if (clr_pcount) begin

//insert synchronous reset actionend else if (bit_en) begin

//insert synchronous clocked action/. end


assign prbs = …………;         //assign MSB of prbsreg to output


Complete the above SV description of the ‘prbsgen’ module and verify its correct operation by performing a behavioural simulation using the Vivado Simulator (after adding it to the project). It may be beneficial to combine the ‘prbsgen’ and ‘divclk’ modules into a test-module, given that ‘bit_en’ is generated by the latter. Add the relevant signals to the wave window and use the ‘Force’ commands (or the test-module) to stimulate the inputs.

Experiment with different values of ‘prbsgen’ parameters ‘N’ and ‘TapMask’, suitable feedback tap values may be found by searching the internet.Capture the waveform results in order to clearly show correct operation of the module and insert them, along with the source listing, into your report. Comment on the results obtained[10 marks]

As shown in figure 2b, a pair of Exclusive-OR gates along with a D-type Flip-flop are used to generate the Manchester encoded bit-stream ‘man_tx’. Additional flip-flops are included to synchronise the remaining outputs to the system clock. The signal labelled ‘error’ in figure 2b is Exor’d with the ‘prbs’ output of the ‘prbsgen’ module before being further Exor’d with the ‘bit_clk’ signal from the clock divider module. Explain the function of this part of the Manchester Encoder sub-system (the two Exor gates and the D-type flip-flop they feed).

[10 marks]

The module named ‘Div_Error’ in figure 2b operates as follows:

  1. The input named ‘Error_on’ is used to turn on the error pulses, if it is logic-0 the ‘error’ output is at logic-0. If ‘Error_on’ is at logic-1 the error pulses are enabled.
  1. The 3-bit input named ‘ErrRate’ controls the interval (in terms of NRZ data bits) between ‘error’ bits (which invert one bit of the NRZ data stream) in order to simulate a range of bit-error rates, as per the following table:
ErrRateBits between errors*Bit Error Rate (%)

*1 less than bits per error

  • An internal counter is incremented each time input ‘bit_en’ is asserted and resets to zero after reaching the required ‘bits between errors’ value.
  1. All sequential elements are reset asynchronously by ‘rst’ and clocked on the positive-edge of ‘clock’.

Create a SystemVerilog source description for the ‘Div_Error’ block based upon the information provided above. Verify its correct operation by performing a behavioural simulation using the Vivado Simulator, it may be beneficial to combine the ‘Div_Error’ and ‘divclk’ modules into a test-module, given that ‘bit_en’ is generated by the latter.

Capture the waveform results in order to clearly show correct operation of the module(s) and insert them, along with the source listing, into your report. Comment on the results obtained.

[15 marks]

Combine the modules created and verified above together, in order to create a SystemVerilog source description for the ‘ManchTrans’ block, using figure 2b as a guide. Attempt to use consistent signal and port names throughout, so that automatic port connections can be exploited, shown by the following line of SV source text:

Div_Error DE1(.*);      //instantiation of ‘Div_Error’ module with auto-­‐connection

The module header for ‘ManchTrans’ is provided below:

module ManchTrans #(parameter N = 4, TapMask = 4’b1100) //passed to ‘prbsgen’ (input logic clock, rst, clr_pcount,

input logic Error_on,

input logic [2:0] ErrRate,

output logic transmit_bit_enable, nrz, man_bit_clk, man_tx, output logic [N-­‐1:0] Pcount);

the above module header includes parameters to set the length and feedback tap positions of the

PRBSG, for initial simulation purposes these will be set to the following values:

Length, N = 4

Feedback taps, TapMask = 4’b1100

Include a SystemVerilog source listing for the ‘ManchTrans’ module(s) in your report, neatly presented using appropriate use of reserved word highlighting and indentation.

[10 marks]

Task 2 – Behavioural Simulation of the ‘ManchTrans’ block

Appendix A contains a listing for a test-module to be used to verify the ‘ManchTrans’ module. Create a new simulation source file named ‘’ using the procedure described below and copy the text from Appendix A into the file, reformatting it as required. Add the source file as a ‘simulation source’ to the Vivado® project created earlier. Ensure all of the SystemVerilog design source files you have created in task 1 are also added to the project as design files. The following screenshot shows how the properties of any source file can be viewed and changed if required:

Click on the ‘Add Sources’ tool button in the Project Manager group and then select ‘Add or Create Simulation Sources’ from the ‘Add Sources’ window.

Click on ‘Create File’ and enter/select the fields as shown below:

Click ‘OK’, then ‘Finish’ then ‘OK’ again to skip the ‘Define Module’ step. An almost empty SV test-module source file will be added to the ‘Simulation Sources’ group. Open this file and copy/paste the test-module source from the Appendix into it. It may be necessary to edit the text to tidy up the formatting.

Run a behavioural simulation of the design and capture the waveform results, including all relevant signals (it may be necessary to set the ‘test_ManchTrans’ module as the top-level simulation module, if other test-modules are already present in the project)

The initial simulation sets the error control inputs, ‘Error_on’ and ‘ErrRate’ to zero. Try changing these to: ‘Error_on = 1’b1’ and ‘ErrRate = 5’. Rerun the simulation (Run – Relaunch Simulation) and record/explain the simulation results (refer to the Bit-Error Rate table provided in Task 1).

Copy and paste clear images of the simulation results, showing a variety of views (full and zoomed-in) to clearly confirm the operation of the ‘ManchTrans’ module. Write down brief comments to explain the waveforms presented.

[10 marks]

Maddox Smith

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