Circuit Diagram Assignment Help
- Short Answer. ).
- Draw a schematic for a CMOS gate that implements f =ab +ac. You may use an inverter to create the complement of a. There should be three inputs: a, b, c.
- Show how to size the transistors in a. for symmetric DC and AC behavior.
- What is the logical effort of a 4 input NAND gate? Show why?
- What is branching effort? How does it impact the overall path effort calculation?
- What is photo-resist and how is it used in the CMOS manufacturing process?
- Consider a wire with width 360nm, and length 3.6mm. Assume a sheet resistivity of .05 ohms/square. What is the total resistance of the wire? How does this compare to the on-resistance of a 10x inverter in 45nm CMOS.
- (GRAD ONLY)Why did the trend of increasing clock frequency stop in Intel microprocessors? Name one other technique used to increase performance?
- (GRAD ONLY) Why does the ON current of a transistor vary significantly more at Near Threshold than at Super-Threshold? Name one technique from the paper used to mitigate this variation.
- Electrical Behavior (35 points for 558, 40 for 658)
- What is meant by the pitch of a metal layer? Is the pitch of a higher-level metal greater than that of a lower-level metal. Why? 5pts
- Consider two adjacent wires in Metal 1. For a fixed pitch, is it better to widen the wires or increase the spacing in order to reduce delay? Draw a sketch to describe your answer. 10 pts
- What is a repeater? Do higher-level metal wires require more repeaters per unit length than low-level metal wires? Think about R and C of the wires. 5pts
- Show how coupling noise onto a wire could cause a Noise Margin violation in a subsequent inverter. Sketch a waveform. 5pts
- GRAD ONLY Consider the same circuit as in part a. but now minimize for power. 5pts
- (35 points for 558, 40 for 658)
- Draw a schematic for the following layout. Label A,S,B and Z. 15pts
Lucky for you this circuit only uses one metal layer.
- Indicate the transistor widths on the schematic, assuming a 45nm feature size.5 pts.
- Indicate the well-ties in the layout 5 pts
- Draw a cross-section of the circuit along line B 10 pts
- . (GRAD ONLY) What is the worst-case delay input transition for the circuit 5 pts