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Solution:-

The  two 2-bit as A[1:0] and B[1:0]

Therefore for the 2-bit comparator we have four inputs A[1],A[0] and B[1],B[0] and three outputs  OEQU ( = 1 if two numbers are equal i.e if all A[i]=B[i]) , OGRE (= 1 when A > B) and OLES (= 1 when A < B)

TRUTH TABLE:

A[1]A[0]B[1]B[0]OGREOEQUOLES
0000010
0001001
0010001
0011001
0100100
0101010
0110001
0111001
1000100
1001100
1010010
1011001
1100100
1101100
1110100
1111010

Prob 2.

Solution:-

ConditionA[1]B[1]A[0]B[0]olesoequogre
Top 2 bits

Different

10XX001
01XX100
Top 2 bits

Same,

0

1

0

1

10001
Bottom 2

Different

0

1

0

1

01100
A = B0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

C1C2C3

Where C1,C2,C3 are the outputs OLES,OEQU,OLES respectively of the first comparator.

By observing the above truth table we can get the following equations:

 

Prob  3.

Solution:-

Truth table:

Message      Even parity bit     Checker bit

X  Y  Z                 P                          C

0  0  0                   0                           0

0  0  1                   1                           0

0  1  0                   1                           0

0  1  1                   0                           0

1  0  0                   1                           0

1  0  1                   0                           0

1  1  0                   0                           0

1  1  1                   1                           0

The circuit can now be derived by drawing the K-map for the output.

From this the minimal output equation is

This function can be implemented using exclusive-or gates. The schematic of the parity generator circuit is shown in F

Figure 1: Parity bit genera

Similarly the checker circuit can be designed using XOR gates, where  and the circuit is shown in Figure 2.

Figure 2: Checker circuit

Now the parity bit generator and the checker circuit can be combined into one circuit for simplicity. The final schematic of the circuit is shown in Figure 3.

Figure 3: Combined schematic of both parity bit generator and checker circuit

Since there are total 16 inputs the first four inputs are applied to the first MUX,the second four

Inputs.The second 4 inputs are applied to second 4:1 MUX,the third 4 inputs to the third 4:1 MUX and fourth 4 inputs to the fourth 4:1 MUX.Four select inputs are required.Select inputs C and D are applied to  select lines S1 and S0 of respective MUXes.The outputs of thes 4 MUXes are connected as data inputs to the fifth 4:1 MUX and select inputs A and B are applied to S1 and S0 of that MUX.

 Prob 5.

Solution:

A1A0B1B0Z3Z2Z1Z0
0000
0001
0010
0011
0100
01011
01101
0111  11
1000
10011
  10101
101111
1100
110111
111011
111111

Solving by K-map we get

z3 = A1A0B1B0

z2 = B1A0b1 + A1B1B0

A1A0B1B0Z3Z2Z1Z0
0000
0001
0010
0011
0100
01011
01101
011111
1000
10011
10101
101111
1100
110111
111011
111111 

 

 

 

Solving by K-map we get

 

z1 = a1A0b0 + a1B1b0 + A1a0b1 + a0b1B0

Prob 6.

Solution:-

In the given circuit if [M,P]=[0,1] for both the MUXes line no. 1 will be selected.

For upper MUX carry-out (CO) of lower full adder is connected to line 1 and

For lower MUX  sum output (S) of the lower full adder is connected to line 1.

So it performs the same function as a single full adder.

i.e. output F for lower MUX is same as sum output (S) and output CO for upper MUX is same as carry output (CO) of lower full adder.

Prob 8.

sOLUTION:

Sequential Logic

A 4-bit Johnson counter made from four D-type flip-flops is shown in figure

4-bit Johnson counter.

Truth table for Johnson counter

 

Maddox Smith

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